1. Field of the Invention
The present invention relates to integrated circuit (IC) design methods and systems and, particularly, to IC design method and system by timing-driven block placement that imposes timing conditions such as line delay and signal transmission synchronous as constraints and designs IC in consideration of these constraints.
2. Description of Related Art
Recently, as the product-life cycle of electronic equipment using an IC shortens and the product performance improves, reduction in design time and improvement in design quality are required for design automation technology.
However, in IC design automation systems with a top-down approach, path delay expected by the logic design in the upstream of the design process, and path delay of the layout result in the layout design in the downstream of the design process differ in some cases. The path delay in the layout result can be longer than the expected path delay.
If the layout results do not satisfy timing constraints, the circuit configuration should be changed. Thus, it is necessary to repeat the circuit composition, layout, and so on until the layout result that meets the timing constraints is obtained. This increases the IC development period and costs.
To overcome the above problem, a timing-driven technique has been proposed recently. The timing driven technique associates the logic design process in the upstream and the layout design process in the downstream, and imposes the constraint to satisfy the path delay expected in the logic design in the upstream on the layout design in the downstream. This eliminates the difference between the path delay of the layout result and the expected path delay in the upstream.
The timing driven technique is explained hereinafter with reference the drawings. FIG. 1 is a conceptual diagram showing information input or output in a conventional timing-driven placement process.
Generally in conventional timing-driven placement processes, a placement processor 205 receives layout information 201, timing constraint 202, and clock skew information 203. The layout information 201 includes net list, block information, background information, I/O buffer placement information, and hard macro placement information. The timing constraint 202 defines delay on all sequential circuit paths so as to satisfy expected delay calculated in the logic design. The clock skew information 203 includes clock skew information of all sequential circuits The placement processor 205 determines optimal placement position of each block in such a way that path delay Tr between specific sequential circuits satisfies the setup and hold time requirements represented by the following expressions (1) and (2), and outputs a placement result 204.Tr<Ti−Si−St  (1)Tr>Si+Ht  (2)where Ti is an operating period of a specific sequential circuit path extracted from the timing constraint 202, Si is clock skew between sequential circuits extracted from the clock skew information 203, St is a setup time at an end point sequential circuit, and Ht is a hold time at the endpoint sequential circuit. At this time, a fixed value which is uniform in clock domains is defined to the clock skew information 203 of all sequential circuits.
A technique that is widely used recently to reduce a layout time uses a data chip with a preformed clock circuit having a tree structure with equal load and equal line length. This technique can eliminate the need for clock distribution in the layout process.
FIG. 2 shows the chip structure with a preformed clock circuit having a tree structure with equal load and equal line length. In this chip, the clock circuit having clock buffers 206 to 228 and a clock line 229 is preformed. The clock circuit includes the output line from the final-stage clock buffer 218 connected to a sequential circuit. The area including the end of the output line from the final-stage clock buffer 218 is a sequential circuit placement area 231. It is thereby possible to connect a sequential circuit to a clock simply by placing the sequential circuit in any position within the sequential circuit placement area 231 in the placement process. The area other than the sequential circuit placement area 231 is a combinational circuit placement area 230.
However, the present invention has recognized that use of the above structure for the conventional timing-driven placement process causes clock skew to vary widely by the position of the sequential circuit. This causes a wide difference between a clock skew value expected for the placement process and an actual clock skew value calculated from the placement result.
For example, FIG. 3 shows data transmission between sequential circuits 232 and 233 to which a clock is supplied from the final-stage clock buffers 214 and 217, respectively, of FIG. 2. In this case, a branch point of the clock is at the output terminal of a root clock buffer 206. Thus, the clock path from the root of the clock to each of the sequential circuits is totally different. The clock is thereby greatly affected by variation in chip, which increases clock skew.
On the other hand, FIG. 4 shows data transmission between the sequential circuits 232 and 233 to which a clock is supplied from the final-stage clock buffer 214 of FIG. 2. In this case, a branch point of the clock is at the output terminal of the final-stage clock buffer 214. Thus, the clock path from the root of the clock to each of start and end point sequential circuits is substantially the same. The influence of the variation in chip is thereby very low, causing substantially no clock skew.
If the clock skew widely varies by the position of the sequential circuit, it is difficult to obtain the placement result that meets the setup and hold time requirements. For example, when an actual clock skew value between sequential circuits calculated from the placement result is greater than a clock skew value preset to the timing-driven placement process, even if the placement processor 205 controls the placement to satisfy the expressions (1) and (2), timing analysis based on the actual clock skew after the placement is likely to show failure to meet the setup and hold time requirements.
An approach for the path that satisfies the setup and hold time requirements in the placement processor 205 to completely avoid the problem which is not given by the timing analysis based on the actual clock skew value after the placement is to set the value of the clock skew between sequential circuits applied to the timing-driven placement process to a maximum value of the clock skew calculated from the preformed clock circuit. However, the present invention has recognized that, since the value of clock skew is estimated to be greater than an actual value for most sequential circuit paths in this case, it is difficult to satisfy the expressions (1) and (2) in all the sequential circuit paths within the timing-driven placement processor.